A multi-gigabit DLL-based CMOS PWM demodulator using delay vernier sampler

A CMOS PWM demodulator for multi-gigabit data rate is described. It uses a DLL and a delay vernier sampler to demodulate PWM signal with periodic rising edges. The sampler utilizes delay vernier technique to achieve a very fine sampling resolution. The proposed circuit was designed using AMS 0.35μm process parameters. The 4-bit encoded PWM signal is used in simulation. Simulation results show that the circuit is capable of demodulate and recover data at a data rate of 3 Gbps. The demodulator dissipates 66 mW at 3.3 V supply voltage.