An efficient VLSI architecture for the Rader Algorithm based DFT prime-factor

In this paper, we improve the DFT architecture, when transform size N is prime, to make it more efficient. Compare to the traditional structure using the Rader Algorithm, the proposed architecture changes from sequential output to parallel outputs. Consequently, the latency is reduced from 15 clock cycles to 8 clock cycles in the case of 7-point DFT, and from 2N+1 to N+1 in the case of N-point DFT. Moreover, the number of the input registers is also about 40% reduced.