Data reuse in sliding window operations base on storing block targeted hardware compilation

A memory architecture is proposed to automatically explore the design space consisting of data reuse for sliding window applications, in the context of FPGA-targeted hardware compilation. Sliding window operator is widely used in the typical applications on reconfigurable system, such as image processing, pattern recognition and digital signal processing, etc. But the sliding window circuit generated by reconfigurable compiler system is not so efficiency, limited by redundant storage, waiting operation and so on. In this paper, we present a block-based storage data reuse method to increases data throughput in sliding window applications. Through parallel access the window data, our method can reduce memory access time and improve the performance of hardware circuit. Experiments show that in three typical applications of sliding window, this approach can achieve accelerating of sliding window circuit, the performance of the program enhances 6.5-7.9 times.