DocumentCode
519891
Title
Subsystem of technological editing of topology of plated circuits
Author
Panchak, Roman ; Kolesnik, Konstantin
Author_Institution
CAD/CAM Dept., Lviv Polytech. Nat. Univ., Lviv, Ukraine
fYear
2010
fDate
20-23 April 2010
Firstpage
121
Lastpage
122
Abstract
The features of work of subsystem of the automatic editing of topology of PCBS are examined in this work. The considered subsystem allows to execute in the automatic mode editing above topology of PCBS, with the purpose of minimization of an amount of the technologically justified places with a minimum clearance.
Keywords
network topology; printed circuits; plated circuit topology; printed circuits board; technological editing; Bonding; Circuit topology; Databases; Electronic components; Frequency; Manufacturing; Minimization; Printed circuits; Shape measurement; Size measurement; manufacturability of PCB; topology of PCB;
fLanguage
English
Publisher
ieee
Conference_Titel
Perspective Technologies and Methods in MEMS Design (MEMSTECH), 2010 Proceedings of VIth International Conference on
Conference_Location
Lviv
Print_ISBN
978-1-4244-7325-0
Electronic_ISBN
978-966-2191-11-0
Type
conf
Filename
5499307
Link To Document