A 134 GHz ${+}4$ dBm Frequency Doubler at $f_{\max }$ in 130 nm CMOS

A +4 dBm 134 GHz frequency doubler operating at the maximum oscillation frequency (fmax) of the technology is shown in an IBM 130 nm CMOS process. The doubler is implemented in a balanced topology, driven by a chain of stacked Class-AB amplifiers, and generates the highest reported power in 130 nm CMOS beyond 100 GHz. A theoretical study of frequency doublers is presented including scaling trends across frequency and CMOS technology nodes.