A low-power SRAM using bit-line charge-recycling technique

Author

Keejong Kim ; Mahmoodi, Hamid ; Roy, Kaushik

Author_Institution

Purdue Univ., West Lafayette, IN, USA

fYear

2007

fDate

27-29 Aug. 2007

Firstpage

177

Lastpage

182

Abstract

We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13μm CMOS and measurement results show 88% reduction in total power compared to the conventional SRAM (CON-SRAM) at VDD=1.5V and f=100MHz.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit manufacture; low-power electronics; power cables; CMOS; CON-SRAM; adjacent bit-line capacitance; bit-line charge-recycling technique; data retention; differential voltage swing; frequency 100 MHz; low-power SRAM; memory cells; power lines; power supply lines; size 0.13 mum; test-chip; voltage 1.5 V; CMOS technology; Capacitance; Chromium; Circuits; Energy consumption; Power dissipation; Power measurement; Power supplies; Random access memory; Voltage; SRAM; charge-recycling; low power; process variation; write margin; write power;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Conference_Location

Portland, OR

Electronic_ISBN

978-1-59593-709-4

Type

conf

DOI

10.1145/1283780.1283819

Filename

5514314