Low-power H.264/AVC baseline decoder for portable applications

In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180 nm technology, the proposed design is able to decode QCIF 30 fps at 1.5 MHz. It consumes 698 μW operated under 1.8 V power supply. The decoder contains 169 k logic gates and 2.5 KB on-chip SRAM. The total chip area is 4.4 × 4.4 mm² in a CQFP 208 package. The low-power and real-time features make our design ideal for portable applications where video quality is often traded off for energy.