Design of DDR2 SDRAM controller for video post processing pipeline

To satisfy real-time high-definition video processing requirement of video post processing pipeline, this paper proposes a novel DDR2 controller design which efficiently and selectively integrates the DDR2 SDRAM controller created by Xilinx MIG (Memory Interface Generator) and the control module of MPMC (Multi-Port Memory Controller). The DDR2 controller is implemented as a part of the whole pipeline of a video post processing processor which has been verified in the Xilinx XUP5 Lxt-110t FPGA. Many experimental results have shown that this DDR2 controller demonstrates properties of low-latency, high-throughout, high bus utilization compared to the individual MIG and MPMC controllers, and meets the real-time HD processing requirements for this video post processing processor.