Formal modeling and reasoning for reliability analysis

Transient faults in logic circuits are an important reliability concern for future technology nodes. In order to guide the design process and the choice of circuit optimization techniques, it is important to accurately and efficiently model transient faults and their propagation through logic circuits, while evaluating the error rates resulting from transient faults. To this end, we give an overview of the existing formal methods for modeling and reasoning about transient faults. We describe the main aspects of transient fault propagation and the advantages and drawbacks of different approaches to modeling them.