DocumentCode
523619
Title
An efficient dynamically reconfigurable on-chip network architecture
Author
Modarressi, Mehdi ; Sarbazi-Azad, Hamid ; Tavakkol, Arash
Author_Institution
Comput. Eng. Dept., Sharif Univ. of Technol., Tehran, Iran
fYear
2010
fDate
13-18 June 2010
Firstpage
166
Lastpage
169
Abstract
In this paper, we present a reconfigurable architecture for NoCs on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications at run-time. The run-time topology construction mechanism involves monitoring the network traffic and changing the inter-node connections in order to reduce the number of intermediate routers between the source and destination nodes of heavy communication flows. This mechanism should also preserve the NoC connectivity. In this paper, we first introduce the proposed reconfigurable topology and then address the problem of run-time topology reconfiguration. Experimental results show that this architecture effectively improves the NoC power and performance over the existing conventional architectures.
Keywords
Computer architecture; Delay; Energy consumption; Measurement; Network topology; Network-on-a-chip; Optimization methods; Runtime; Telecommunication traffic; Wires; NoC; performance; power; reconfigurable; topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
978-1-4244-6677-1
Type
conf
Filename
5522696
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