Node addition and removal in the presence of don´t cares

This paper presents a logic restructuring technique named node addition and removal (NAR). It works by adding a node into a circuit to replace an existing node and then removing the replaced node. Previous node-merging techniques focus on replacing one node with an existing node in a circuit, but fail to replace a node that has no substitute node. To enhance the node-merging techniques on logic restructuring and optimization, we propose an NAR approach in this work. We first present two sufficient conditions that state the requirements of added nodes for safely replacing a target node. Then, an NAR approach is proposed to fast detect the added nodes by performing logic implications based on these conditions. We also apply the NAR approach to circuit minimization together with two techniques: redundancy removal and mandatory assignment reuse. We conduct experiments on a set of IWLS 2005 benchmarks. The experimental results show that our approach can enhance the state-of-the-art ATPG-based node-merging approach. Additionally, our approach has a competitive capability of circuit minimization with 44 times speedup compared to a SAT-based node-merging approach.