DocumentCode
523871
Title
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent
Author
Hazra, Aritra ; Mitra, Srobona ; Dasgupta, Pallab ; Pal, Ajit ; Bagchi, Debabrata ; Guha, Kaustav
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
fYear
2010
fDate
13-18 June 2010
Firstpage
773
Lastpage
776
Abstract
Recent research has indicated ways of using UPF specifications for extracting valid low-level control sequences to express the transitions between the power states of individual domains. Today there is a disconnect between the high-level architectural power management strategy which relates multiple power domains and these low-level assertions for controlling individual power domains. In this paper we attempt to bridge this disconnect by leveraging the low-level per-domain assertions for translating architectural power intent properties into global assertions over low-level signals. We show that the inter-domain properties created in this manner can be formally verified over the global power management logic.
Keywords
energy management systems; formal verification; high level synthesis; low-power electronics; network synthesis; UPF specification; architectural power intent; formal verification; global power management logic; high level architectural power management strategy; low level assertion; low level control sequence; low level per domain assertion; low level signal; power domain; power state; unified power format; Circuits; Energy management; Formal verification; Hardware design languages; Logic; Permission; Power control; Power engineering and energy; Regulators; Research and development; Assertion; Formal Verification; Power Intent Verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
978-1-4244-6677-1
Type
conf
Filename
5523286
Link To Document