• DocumentCode
    523899
  • Title

    New model-driven design and generation of multi-facet arbiters part I: From the design model to the architecture model

  • Author

    Jou, Jer Min ; Wu, Sih-Sian ; Lee, Yun-Lung ; Chou, Cheng ; Jeang, Yuan-Long

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2010
  • fDate
    13-18 June 2010
  • Firstpage
    258
  • Lastpage
    261
  • Abstract
    Designing of arbiters has become increasingly important because of their wide use in such as multi-processor system-on-a-chips (MPSoCs) and on- or off- chip high-speed cross-bar switches and networks. In this and an accompanying paper [6], we proposed a new systematic model-driven flow for design of the proposed new scalable multi-facet arbiters through a 3-phase process combined with the template-based modular design approach: the design model derivation phase, the architecture model (or template) design phase as well as arbiter hardware implementation and generation phase. Here, we described the phase 1 of the design flow of how to induce an arbiter design model in detail by careful analysis of arbiter design issues and systematic design space exploring the construction of the model. Then, we continue to discuss the phase 2 of how to derive an architecture model or template using the reusability, modularity and expansibility techniques. With both the design and architecture models, designers can easily design or at least understand and thus choose many kinds of different but better arbiters efficiently. The phase 3 is described in the accompanying paper [6]. To our knowledge, this is the first time that such a systematic model-driven design approach is proposed for the practical hardware design.
  • Keywords
    asynchronous circuits; logic design; arbiter hardware generation phase; arbiter hardware implementation phase; architecture model; architecture model design phase; design model; design model derivation phase; expansibility technique; model-driven design; modularity technique; multifacet arbiter generation; multiprocessor system-on-a-chips; reusability technique; template-based modular design approach; Algorithm design and analysis; Arithmetic; Communication switching; Computer architecture; Computer science; Design engineering; Hardware; Space exploration; Switches; System-on-a-chip; Model-driven design flow; architecture model/template; design model; design space; granularity; multi-facet arbiter;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2010 47th ACM/IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4244-6677-1
  • Type

    conf

  • Filename
    5523355