DocumentCode
524009
Title
Network on chip design and optimization using specialized influence models
Author
Ababei, Cristinel
Author_Institution
Electr. & Comput. Eng. Dept., North Dakota State Univ., Fargo, ND, USA
fYear
2010
fDate
13-18 June 2010
Firstpage
625
Lastpage
626
Abstract
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-on-Chip (NoC). Our goal is to construct a versatile modeling framework that will help in the development and analysis of distributed and adaptive features for NoCs. As an application testbench, we use this framework to construct a design methodology for dynamic voltage and frequency scaling (DVFS). We also point out similarities of the proposed model with backpressure mechanisms that could be potentially exploited toward enhanced models for estimation and optimization of NoCs.
Keywords
circuit optimisation; integrated circuit design; network-on-chip; power aware computing; NoC; backpressure mechanisms; dynamic voltage frequency scaling; network on chip design; optimization; Algorithm design and analysis; Computer networks; Design engineering; Design optimization; Dynamic voltage scaling; Frequency; Integrated circuit modeling; Neodymium; Network-on-a-chip; Testing; Influence model; Network on Chip; VFI design style;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
978-1-4244-6677-1
Type
conf
Filename
5523572
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