DocumentCode :
524028
Title :
Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization
Author :
Veetil, Vineeth ; Chang, Yung-Hsu ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
EECS Dept., Univ. of Michigan, Ann Arbor, MI, USA
fYear :
2010
fDate :
13-18 June 2010
Firstpage :
793
Lastpage :
798
Abstract :
To exploit the benefits of throughput-optimized processors such as GPUs, applications need to be redesigned to achieve performance and efficiency. In this work, we present techniques to speed up statistical timing analysis on throughput processors. We draw upon advancements in improving the efficiency of Monte Carlo based statistical static timing analysis (MC SSTA) using techniques to reduce the sample size or smart sampling techniques. An efficient smart sampling technique, Stratification + Hybrid Quasi Monte Carlo (SH-QMC), is implemented on a GPU based on NVIDIA CUDA architecture. We show that although this application is based on MC analysis with straightforward parallelism available, achieving performance and efficiency on the GPU requires exposing more parallelism and finding locality in computations. This is in contrast with random sampling based algorithms which are inefficient in terms of sample size but can keep resources utilized on a GPU. We show that SH-QMC implemented on a Multi GPU is twice as fast as a single STA on a CPU for benchmark circuits considered. In terms of an efficiency metric, which measures the ability to convert a reduction in sample size to a corresponding reduction in runtime w.r.t a random sampling approach, we achieve 73.9% efficiency with the proposed approaches compared to 4.3% for an implementation involving performing computations on smart samples in parallel. Another contribution of the paper is a critical graph analysis technique to improve the efficiency of Monte Carlo based SSTA, leading to 2-9X further speedup.
Keywords :
Monte Carlo methods; computer graphic equipment; coprocessors; graph theory; statistical analysis; GPU; SSTA; graph analysis technique; graphics processing units; hybrid quasi Monte Carlo; improved resource utilization; smart Monte Carlo; smart sampling technique; statistical static timing analysis; throughput-optimized processors; Computer architecture; Concurrent computing; Graphics; Monte Carlo methods; Parallel processing; Performance analysis; Resource management; Sampling methods; Throughput; Timing; Graphics Processing Units; Monte Carlo; Statistical timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Conference_Location :
Anaheim, CA
ISSN :
0738-100X
Print_ISBN :
978-1-4244-6677-1
Type :
conf
Filename :
5523603
Link To Document :
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