Title :
Expected system energy consumption minimization in leakage-aware DVS systems
Author :
Jian-Jia Chen ; Thiele, Lothar
Author_Institution :
Comput. Eng. & Networks Lab. (TIK), ETH Zurich, Zurich, Switzerland
Abstract :
The pursuit of energy efficiency is becoming more and more important in hardware and software designs. This research explores energy-efficient scheduling for a periodic real-time task with uncertain execution time in dynamic voltage scaling (DVS) systems with non-negligible leakage/static power consumption. Distinct from the assumption of non-reducible static power consumption in the literature, this paper considers the possibility to reduce it by turning a processor to a dormant mode. We propose an algorithm to derive an optimal frequency assignment to minimize the expected energy consumption without procrastination, while another extended algorithm is developed to apply procrastination scheduling for further energy reduction. Experimental results show that the proposed algorithms can effectively minimize the expected energy consumption.
Keywords :
microprocessor chips; power aware computing; power consumption; scheduling; dormant mode; dynamic voltage scaling systems; energy reduction; energy-efficient scheduling; expected system energy consumption minimization; hardware designs; leakage-aware DVS systems; nonnegligible leakage static power consumption; optimal frequency assignment; processor energy consumption; software designs; Dynamic scheduling; Dynamic voltage scaling; Energy consumption; Energy efficiency; Hardware; Processor scheduling; Real time systems; Scheduling algorithm; Software design; Voltage control; dynamic voltage scaling (dvs); expected energy consumption minimization; leakage-aware scheduling; probability;
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-8634-2
Electronic_ISBN :
978-1-60558-109-5
DOI :
10.1145/1393921.1394006