• DocumentCode
    524099
  • Title

    Word-interleaved cache: an energy efficient data cache architecture

  • Author

    Kalyan, T. Venkata ; Mutyam, Madhu

  • Author_Institution
    CVEST, IIIT Hyderabad, Hyderabad, India
  • fYear
    2008
  • fDate
    11-13 Aug. 2008
  • Firstpage
    265
  • Lastpage
    270
  • Abstract
    We propose a novel energy-efficient data cache architecture, namely, word-interleaved (WI) cache. In theWI cache, a cache block is distributed uniformly among the different cache ways and each line of a cache way holds some words of the block. This distribution provides an opportunity to activate/deactivate the cache ways based on the requested address´s offset, thus minimizing the overall cache access energy. For a 4-way set associative cache of size 16KB and blocksize 32B, the proposed technique accomplishes dynamic energy savings of 54.2% without considering fast hits and 62.3% when fast hits are considered, with small performance degradation and negligible area overhead.
  • Keywords
    cache storage; memory architecture; Word-interleaved cache; cache memory; data cache architecture; Cache memory; Decoding; Degradation; Delay; Energy consumption; Energy efficiency; High performance computing; Multiplexing; Power dissipation; System performance; cache; low power techniques; offset based decoding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
  • Conference_Location
    Bangalore
  • Print_ISBN
    978-1-4244-8634-2
  • Electronic_ISBN
    978-1-60558-109-5
  • Type

    conf

  • DOI
    10.1145/1393921.1393991
  • Filename
    5529040