A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes

Author

Jie Jin ; Chi-Ying Tsui

Author_Institution

Dept. of Electr. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2008

fDate

11-13 Aug. 2008

Firstpage

253

Lastpage

258

Abstract

This paper presents a low power LDPC decoder design based on reducing the amount of memory access. By utilizing the column overlapping of the LDPC parity check matrix, the amount of access for the memory storing the posterior values is minimized. In addition, a thresholding decoding scheme is proposed which reduces the memory access by trading off the error correcting performance. The decoder was implemented in TSMC 0.18μm CMOS process. Experimental results show that for a LDPC decoder targeting for IEEE 802.11n, the power consumption of the memory and the decoder can be reduced by 72% and 24%, respectively.

Keywords

CMOS integrated circuits; IEEE standards; decoding; error correction codes; parity check codes; wireless LAN; CMOS process; IEEE 802.11n LDPC codes; LDPC decoder implementation; LDPC parity check matrix; TSMC; error correcting performance; low power LDPC decoder design; low power layered decoding architecture; memory access reduction; memory storage; power consumption; thresholding decoding scheme; Computer architecture; Costs; Energy consumption; Error correction; Hardware; Iterative algorithms; Iterative decoding; Message passing; Parallel architectures; Parity check codes; low power; low-density parity-check code; thresholding;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Conference_Location

Bangalore

Print_ISBN

978-1-4244-8634-2

Electronic_ISBN

978-1-60558-109-5

Type

conf

DOI

10.1145/1393921.1393989

Filename

5529042