A tutorial on test power

Both average power and peak power specifications of a circuit pose serious problems for the prevalent test methods like scan and built-in self-test. This tutorial discusses the problems and solutions for minimizing power dissipation in these test procedures. Hardware approaches and test vector optimization methods are outlined. Power-constrained testing of core-based systems is discussed. Finally, an open problem of finding an efficient test for verifying the power specification of a system is formulated. Today´s electronic systems are complex, fast, and energy efficient. Power is a circuit design criteria, added to the previous list of area, delay and testability. Controlling test power and minimizing test time requires tradeoffs. Design for testability methods like scan and random-pattern self-test use non-functional test inputs that must conform to circuit specifications on average power (energy consumption) and peak power. Test power has thus become an active area of research, innovation and practice. Electronic circuits should dissipate no more power or energy than they are designed for. In testing of circuits cost and quality are the requirements and high fault coverage can lead to long, often nonfunctional, test sequences. Such tests generate substantially higher signal activity and can potentially cause an otherwise good circuit to fail due to excessive power dissipation. Tests are, therefore, run at a slower speed, incurring longer test time and higher test cost. This extra cost of testing does not completely solve the test power problem. The slow speed test can contain high activity vectors that would cause excessive supply current surges. Once again a perfectly good circuit can potentially fail during test due to conditions such as power droop, ground bounce and hot spots.