Title :
Analytical results for design space exploration of multi-core processors employing thread migration
Author :
Rao, Ramesh ; Vrudhula, Sarma ; Berezowski, Krzysztof
Author_Institution :
Consortium for Embedded Syst., Arizona State Univ. (ASU), Tempe, AZ, USA
Abstract :
Migrating threads away from the hot cores in a multicore processor allows them to operate at up to higher speeds. While this technique has already attracted a lot of research effort, the majority of thread migration studies are simulation-based. Although they are valuable for micro-architectural level optimization, they require prohibitively long simulation times, and hence have limited value for early design space exploration. We derive closed form expressions for the steady-state throughput of a multicore processor that employs thread migration and throttling for thermal management. These expressions can be evaluated under a millisecond (vs days for cycle-accurate simulation), and allow designers greater flexibility in evaluating the trade-offs involved in implementing thread migration on-chip. We also developed a system-level power/thermal simulator that we used to validate the analytical results.
Keywords :
coprocessors; multi-threading; multiprocessing systems; power aware computing; design space exploration; multicore processors; system level power simulator; system level thermal simulator; thermal management; thread migration on-chip; Clocks; Embedded system; Frequency; Multicore processing; Power system management; Space exploration; Temperature; Thermal management; Throughput; Yarn; analytical; leakage dependence on temperature; thermal management; thermal model; thread migration; throttling; throughput;
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-8634-2
Electronic_ISBN :
978-1-60558-109-5
DOI :
10.1145/1393921.1393981