Title :
Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion
Author :
Akl, C.J. ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies (CACS), Univ. of Louisiana at Lafayette, Lafayette, LA, USA
Abstract :
A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-Vth keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design.
Keywords :
CMOS logic circuits; combinational circuits; integrated circuit design; logic design; short-circuit currents; MTCMOS adder; MTCMOS combinational logic circuit design; excessive short circuit current; internal circuit nodes; keeper insertion technique; spurious glitch minimization; wakeup latency reductions; word length 16 bit; Adders; Combinational circuits; Delay; Leakage current; MOS devices; Metastasis; Permission; Recycling; Runtime; Very large scale integration; leakage power; mode transition; power gating;
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-8634-2
Electronic_ISBN :
978-1-60558-109-5
DOI :
10.1145/1393921.1393942
