On leakage currents: sources and reduction for transistors, gates, memories and digital systems

In only 5 years, leakage developed from an academic corner phenomenon to a central problem of embedded system design. In sub 90nm designs the leakage power is already exceeding the dynamic power. The intention of this tutorial is to first review the mechanisms causing leakage and the parameters and imperfections causing leakage variation as the dependencies on physical parameters as temperature, voltage levels, device geometry, doping levels, etc. Afterwards, the state-of-the-art in leakage reduction and management methodologies is presented with a first focus on transistor design including well engineering, high-k, strained silicon, SGOI devices, fully depleted ultra thin body SOI, as well as FinFETs. Then, technical aspects on the leakage management techniques power gating, body and supply voltage scaling and minimum leakage vector are discussed. Finally, low leakage SRAM cell design and different cache decay techniques are presented.