DocumentCode
52444
Title
Topology-Aware Adaptive Routing for Nonstationary Irregular Mesh in Throttled 3D NoC Systems
Author
Kun-Chih Chen ; Shu-Yen Lin ; Hui-Shun Hung ; Wu, An-Yeu Andy
Author_Institution
Inst. of Electrics Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
24
Issue
10
fYear
2013
fDate
Oct. 2013
Firstpage
2109
Lastpage
2120
Abstract
Three-dimensional network-on-chip (3D NoC) has been proposed to solve the complex on-chip communication issues in future 3D multicore systems. However, the thermal problems of 3D NoC are more serious than 2D NoC due to chip stacking. To keep the temperature below a certain thermal limit, the thermal emergent routers are usually throttled. Then, the topology of 3D NoC becomes a Nonstationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, some routing algorithms had been proposed in the previous works. However, the network still suffers from extremely traffic imbalance among lateral and vertical logic layer. In this paper, we propose a Topology Aware Adaptive Routing (TAAR) to balance the traffic load for NSI-Mesh in 3D NoC. TAAR has three routing modes, which can be dynamically adjusted based on the topology status of the routing path. In addition to increasing routing flexibility, the TAAR also increases both vertical and lateral path diversity to balance the traffic load. Compared with the related adaptive routing methods, the experimental results show that the proposed TAAR can reduce 19 to 295 percent traffic loads in the bottom logic layer and improve around 7.7 to 380 percent network throughput. According to our proposed VLSI architecture, the TAAR only needs less than 24.8 percent hardware overhead compared with the previous works.
Keywords
VLSI; microprocessor chips; network routing; network-on-chip; three-dimensional integrated circuits; 2D NoC; 3D multicore system; NSI-mesh; VLSI architecture; complex on-chip communication; logic layer; nonstationary irregular mesh; packet delivery; routing modes; thermal problem; three-dimensional network-on-chip; throttled 3D NoC system; topology aware adaptive routing; topology-aware adaptive routing algorithm; traffic imbalance; vertical logic layer; Complexity theory; Network topology; Nickel; Routing; System recovery; Telecommunication traffic; Topology; 3D IC; 3D NoC; Network-on-chip; transport layer assisted routing;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/TPDS.2012.291
Filename
6327188
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