Implementation of division-free perspective-correct rendering optimized for FPGA devices

Well-known algorithms for perspective-correct rendering of planar polygons in 3D graphic accelerators require per-pixel division. On the other hand, division is an expensive operation in the field programmable gate arrays (FPGAs) in the terms of silicon gates and clock cycles. Fortunately, efficient midpoint algorithms can be used to avoid division. This paper presents the implementation of such an algorithm in the renderer that is optimized for FPGA platform. The renderer implements the midpoint algorithm, which is based on separated computation of the integer parts and the fractional parts of the texture coordinates. The integer parts are used for texture fetching, whereas the fractional parts are used for texture filtering. The midpoint algorithm is embedded in a scanline algorithm. The pipeline architecture is used, resulting in a high clock frequency and high texturing fill-rate. The RTL model of the renderer is developed in VHDL, without the use of family-dependent macros. Therefore, the model is suitable for the reuse in various FPGA families.