DocumentCode :
524714
Title :
Comparative study on Wordlength Reduction and Truncation for low power multipliers
Author :
de la Guia Solaz, Manuel ; Conway, Richard
Author_Institution :
Electron. & Comput. Eng., Univ. of Limerick, Limerick, Ireland
fYear :
2010
fDate :
24-28 May 2010
Firstpage :
84
Lastpage :
88
Abstract :
Power consumption in Digital Signal Processing systems directly relies on the precision of multipliers. As bigger bitwidths are desirable for achieving higher precisions, they result in bigger multipliers with high toggling profiles and higher power figures. In recent years some techniques that trade power for accuracy by removing or reconfiguring blocks of the multiplier have been made available. Choosing the correct technique and implementing it can make a big difference regarding power. This being specially important on low-power battery-operated devices, where a longer life could be preferred to a higher output precision. Operand Reduction and Truncated multipliers are two such techniques. They are reviewed in this paper and their effectiveness and power vs accuracy exchange profiles are compared and analyzed for ASIC design via simulation. Comparative results are presented after applying both techniques to a 16-bit Wallace tree-based multiplier synthesized in 90nm low power standard cells.
Keywords :
Application specific integrated circuits; Digital signal processing; Energy consumption; Leakage current; MOS devices; Monitoring; Power dissipation; Power engineering and energy; Power engineering computing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
MIPRO, 2010 Proceedings of the 33rd International Convention
Conference_Location :
Opatija, Croatia
Print_ISBN :
978-1-4244-7763-0
Type :
conf
Filename :
5533392
Link To Document :
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