• DocumentCode
    524823
  • Title

    Accelerating recognition system of leaves on Nios II embedded platform

  • Author

    Liao, Yu-Ping ; Zhou, Hao-Gong ; Fan, Gang-Ren

  • Author_Institution
    Ching Yun Univ., Jhongli, Taiwan
  • Volume
    1
  • fYear
    2010
  • fDate
    5-7 May 2010
  • Firstpage
    334
  • Lastpage
    337
  • Abstract
    In this paper, we present an efficient HW/SW codesign architecture of a Recognition System of Leaves. The architecture includes pre-processing modules for the input video signal from the camera and interfaces for the external video memory and the LCD. The recognition of leaf is implemented by hardware in FPGA. By using the five mega-pixel camera included in the Altera DE2-70 kit for input, image processing can be done by FPGA Cyclone II EP2C70F89C6N with ~70,000 LEs on Altera DE2-70 kit. The measurement results can verify HW/SW codesign architecture of leaves recognition easily achieves faster processing performance than the pure SW technique. Using hardware acceleration presents a speed up factor of 7 times over a software implementation.
  • Keywords
    feature extraction; field programmable gate arrays; hardware-software codesign; liquid crystal displays; video cameras; video signal processing; Altera DE2-70 kit; FPGA Cyclone II EP2C70F89C6N; LCD; Nios II embedded platform; external video memory; image processing; leave recognition system; mega pixel camera; software-hardware codesign; video signal; Acceleration; Cameras; Computer architecture; Feature extraction; Field programmable gate arrays; Flowcharts; Hardware; Image processing; Image recognition; Signal processing algorithms; DE2–70; FPGA; Leaf; Nios II; Recognition System;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Communication Control and Automation (3CA), 2010 International Symposium on
  • Conference_Location
    Tainan
  • Print_ISBN
    978-1-4244-5565-2
  • Type

    conf

  • DOI
    10.1109/3CA.2010.5533816
  • Filename
    5533816