A nonlinear placement technique for FPGA-like uniform granularity problem

Uniform granularity design style is widely used in FPGA and structure ASIC designs, which have been dramatically developed in various electronic product fields due to their fast implementation and short time-to-market. Under very deep sub-micron technology nodes, placement becomes a key part of such design style especially in FPGA designs because it affects the following routing efficiency and the final resource requirements very much. At present, the commonly used placement methods are based on the Simulated Annealing. But such kinds of algorithms take too much run time. In this paper, a nonlinear placement technique is proposed to handle the uniform granularity based placement problem, which is especially useful for FPGA placement. In comparison with general nonlinear placement techniques, this technique takes less solving iterations and run-time since the problem has more smooth solution space, and the experimental results compared to FastPlace also show its reasonable quality.