An efficient approach to placement legalization within standard cell circuits

The residual cell overlaps in the global placement are guaranteed to prevent successful routing in very large scale integration physical design. In order to resolve aforementioned illegal placement, the proposed method is divided into two main stages: sorting the cells to be placed according to certain criteria; legalizing the cells one at a time. During legalization, a new term “collision” is introduced to resolve cell overlaps and then we dissect how this term helps to achieve a better placement. Moreover, cells are reassigned to rows through a modified Dijkstra algorithm. Compared to Abacus, empirical validation shows our approach reduces the movement between the cells by 20% to 40% and the CPU time is decreased by 30% to 60% in the ISPD04 IBM Standard Cell Benchmarks with Pads.