Improved design of the multiplier in the digital filter

This paper presents an improved hardware design of multiplier in digital filter utilizing Canonical Signed Digit and Horner´s scheme. Two multiplier structures, a cascaded adder structure and accumulative structure, have been discussed. Both could be used in multiplier implementation, while they occupied different silicon resource in different conditions. By comparing both the structures, the area optimization methodology is found out which can decrease about 10.19% of the total area of whole module.