Optimizing oxide charge balanced devices for Unclamped Inductive Switching (UIS)

Power MOSFET designs have been moving to higher performance particularly in the medium voltage area. (60V to 300V) New designs require lower Specific On-resistance while not sacrificing Unclamped Inductive Switching (UIS) capability or increasing turn-off losses. Two charge balance technologies currently address these needs, the PN junction and the Shielded Gate Charge Balance device topologies. This paper will study the impact of drift region as well as other design parameters that influence the shielded gate class of charge balance devices. The optimum design for maximizing UIS capability and minimizing the impact on other design parameters such as R_DSON and switching performance are addressed. It will be shown through TCAD simulation one can design devices to have a stable avalanche point that is not influenced by small variations within a die or die-to-die that result from normal processing. Finally, measured and simulated data will be presented showing a fabricated device with near theoretical UIS capability.