A new 8V – 60V rated low Vgs NLDMOS structure with enhanced specific on-resistance

Author

Ko, Choul-Joo ; Cho, Cheol-Ho ; Lee, Hee-Bae ; Lee, Yong-Jun ; Kim, Min-Woo ; Bang, Sun-Kyung ; Kim, Han-Geon ; Lee, Jae-O ; Shim, Sang-Chul ; Kang, Sun Kyoung ; Kim, Nam-Joo ; Yoo, Kwang-Dong ; Hutter, Lou N.

Author_Institution

Analog Foundry Process Dev. Team, Dongbu Hitek, Bucheon, South Korea

fYear

2010

fDate

6-10 June 2010

Firstpage

245

Lastpage

248

Abstract

We present a new 0.35um BCDMOS technology with a capability of 8 to 60V NLDMOS. The proposed process do not need level shifter, charge pump and boost up due to the same gate oxide thickness with logic 5V CMOS. And the Rsp of the proposed 24V NLDMOS structure is lower by 46% than conventional structure. The process has no thermal budget modification but use simple additional implant step. Also it is compatible with the conventional BCDMOS. The power LDMOS transistors in the process have very competitive performances with NLDMOS in 0.15 - 0.25um BCDMOS technologies.

Keywords

CMOS integrated circuits; power transistors; BCDMOS technology; NLDMOS structure; logic CMOS; power LDMOS transistors; size 0.15 mum to 0.25 mum; size 0.35 mum; specific on-resistance enhancement; voltage 5 V; voltage 8 V to 60 V; CMOS integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Charge pumps; Doping; Driver circuits; Implants; Power semiconductor devices; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on

Conference_Location

Hiroshima

ISSN

1943-653X

Print_ISBN

978-1-4244-7718-0

Electronic_ISBN

1943-653X

Type

conf

Filename

5543978