Cost-effective high-voltage Drain Extended PMOS integration in an advanced STI LBC technology

Different approaches for low-cost high-voltage Drain Extended PMOS (DEPMOS) transistor integration into a thin epitaxy Linear BiCMOS (LBC) technology are presented and discussed. Three device designs processed in an 80 V LDMOS STI LBC technology are shown to extend the operating voltage of the DEPMOS to the desired 75 V range with sufficient margins. In a low-cost implementation using the p-epitaxy layer as drain extension, higher breakdown voltage (BV) is obtained by combining n-buried layer dilution and drain field plating, or by introducing a floating n-buried layer. A high performance device using a through-STI p-type implant chain partially overlapped by backgate well is presented, achieving benchmark specific on-resistance (Rsp) versus BV. The DEPMOS backgate and threshold voltage are optimized without any mask addition.