A novel high voltage SOI LDMOS with Buried N-layer in a self-isolation high voltage integrated circuit

We propose a high voltage silicon-on-insulator (SOI) LDMOS with a Buried N-layer (BN SOI) in a self-isolation SOI high-voltage integrated circuit (HVIC). The ionized donors present in the BN enhance the interface silicon field strength from 10 V/μm of the conventional P-SOI (CP SOI) to 30 V/μm. As a result the maximum electric field in the buried oxide before the adjacent SOI breaks down (named E¡) is increased from 30 V/μm to approx 90 V/μm. Consequently, the blocking voltage (BV) of BN SOI structure is improved by almost 50%. The one-dimensional analytical models for the breakdown voltage in BN SOI and CP SOI devices are presented. Furthermore, a combination of the P-SOI layer with the implanted N-drift region is demonstrated to have enhanced self-isolation which removes the need for deep oxide trenches in Power ICs. Finally, a test self-isolation P-SOI HVIC is fabricated to verify the proposed mechanism by using a simplified process (CMOS compatible), in which a 660 V SOI LDMOS with a patterned buried n-layer is realized.