• DocumentCode
    526609
  • Title

    A multithreaded extension to the OR1200 processor

  • Author

    Zeng, Kun ; Liu, Fudong

  • Author_Institution
    Nat. Lab. for Parallel & Distrib. Process., Nat. Univ. of Defense Technol., ChangSha, China
  • Volume
    5
  • fYear
    2010
  • fDate
    9-11 July 2010
  • Firstpage
    123
  • Lastpage
    127
  • Abstract
    Multithreading is a promising technique that widely used in general purpose processors to hide long latency events such as cache misses. This paper proposes an embedded processor design with multithreading support based on the OR1200 processor. The multithreaded OR1200 processor supports interleaved execution of four threads in a round-robin way. The hardware design is evaluated through RTL-simulation of the verilog code. Results show that the interleaved execution of multiple threads can tolerate the memory latency effectively and an average speed-up of 1.16 can be achieved.
  • Keywords
    embedded systems; hardware description languages; multi-threading; OR1200 processor; RTL simulation; embedded processor design; general purpose processor; hardware design; multithreaded extension; verilog code; Artificial neural networks; Field-flow fractionation; Reduced instruction set computing; Registers; OR1200; interleaved execution; memory latency; multi-threading;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on
  • Conference_Location
    Chengdu
  • Print_ISBN
    978-1-4244-5537-9
  • Type

    conf

  • DOI
    10.1109/ICCSIT.2010.5564694
  • Filename
    5564694