• DocumentCode
    527222
  • Title

    FPGA implementation of Gaussian-distributed pseudo-random number generator

  • Author

    Kang, Minsu

  • Author_Institution
    Dept. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
  • fYear
    2010
  • fDate
    16-18 Aug. 2010
  • Firstpage
    11
  • Lastpage
    13
  • Abstract
    This paper proposes a simple but practical Gaussian-distributed pseudo-random number generator. The features of this generator include a compact architecture based on a decimator connected linear feedback shift register, Gaussian-distributed N-bit random number output, long period of a random number sequence, and good statistical properties.
  • Keywords
    Gaussian distribution; feedback; field programmable gate arrays; random number generation; random sequences; shift registers; FPGA implementation; Gaussian distributed pseudorandom number generator; compact architecture; decimator connected linear feedback shift register; random number sequence; Adders; Clocks; Radiation detectors; FPGA; Gaussian distribution; decimator; random number generator;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Content, Multimedia Technology and its Applications (IDC), 2010 6th International Conference on
  • Conference_Location
    Seoul
  • Print_ISBN
    978-1-4244-7607-7
  • Electronic_ISBN
    978-8-9886-7827-5
  • Type

    conf

  • Filename
    5568516
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=527222