DocumentCode :
527923
Title :
A 1-V 225-nW 1KS/s current successive approximation ADC for pacemakers
Author :
Al-Ahdab, Salim ; Lotfi, Reza ; Serdijn, Wouter A.
Author_Institution :
Biomed. Electron. Group, Delft Univ. of Technol., Delft, Netherlands
fYear :
2010
fDate :
18-21 July 2010
Firstpage :
1
Lastpage :
4
Abstract :
An ultra-low-power 1KS/s 8-bit current mode successive approximation (SAR) analog-digital converter (ADC) for pacemakers is presented. The proposed system architecture is designed to achieve a small chip area and ultra low power consumption by using current mode operation. The circuit is realized in a IBM 0.13μm CMOS technology. The simulated power consumption is 225 nW corresponding to a figure of merit of 0.657pJ/conversion-step while operating from a 1 V supply. The power consumption is one of the lowest reported.
Keywords :
CMOS integrated circuits; analogue-digital conversion; current comparators; pacemakers; power consumption; shift registers; IBM CMOS technology; analog-digital converter; current mode operation; current mode successive approximation; pacemakers; power 225 nW; simulated power consumption; size 0.13 mum; ultra low power consumption; voltage 1 V; word length 8 bit; Approximation methods; Integrated circuits; Low power electronics; Mirrors; Pacemakers; Power demand; Transistors; Current ADC; Successive Approximation ADC; low voltage; ultra low power;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ph.D. Research in Microelectronics and Electronics (PRIME), 2010 Conference on
Conference_Location :
Berlin
Print_ISBN :
978-1-4244-7905-4
Type :
conf
Filename :
5587127
Link To Document :
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