Fault resilient intra-die and inter-die communication in 3D integrated systems

Three-dimensional (3D) integration is an emerging technology that enables Systems-on-Chip (3D SoCs) to achieve higher performance at lower power dissipation. In 3D SoCs, the cumulated effects of the intra-die and inter-die interconnect parametric variations lead to high fault rates. In this paper, a fault resilient scheme for inter-die and intra-die communication in 3D SoCs is proposed. Spare wire insertion and error correction codes ensure resilience against permanent and transient faults, respectively. In very-deep sub-micron (VDSM) technologies, single error correction (SEC) capabilities are not enough to ensure the desired reliability levels. In the proposed link, multi-error correction capabilities are achieved by block / interleaved SEC codes. After the interconnect tests, faulty wires are replaced by functional spares, such that the block/interleaved code-words are transmitted only on functional wires. Increasing the wire noise sensitivity and the inter-wire coupling leads to higher error rate. Thus, the codeword size increases and the link area and power overheads go up to ~30%. For high interconnect defect rates the overheads due the configuration logic lead go up to ~300%.