Development of vertical superlattices in silicon for on-chip thermal management

In this paper, we propose a novel approach to on-chip cooling by thermionic emission by using vertical superlattices fabricated directly into the silicon wafer as opposed to conventional planar additive deposition methods used by most other groups. The advantages of this method are (i) significantly lower fabrication costs and (ii) adequate number of superlattice layers translating to higher efficiency. Initial fabrication has been completed on micro-scale `superlattices´ and work on `nano´-superlattices for actual thermionic emission and on-chip cooling are on-going. Measurements of thermal conductivity have been proposed to be made on the completed devices using the 2ω method, which is also described here. Further work will lead to conclusive results from this approach.