Feasibility study of partial-RESET multilevel programming in Phase Change Memories

In this work, staircase-up (SCU) partial-RESET programming in Phase Change Memories is experimentally investigated at both the single cell and the array level. The aim of this work is to highlight advantages and drawbacks of partial-RESET programming from the viewpoint of multilevel (ML) storage, where the cell can be programmed to any among n >2 predetermined different states. Although high reproducibility of the SCU partial-RESET programming curve of a single cell has been observed, the spread over the considered array implies the need for a Program-and-Verify (P&V) approach to achieve the necessary accuracy for ML storage. The feasibility of SCU P&V partial-RESET programming is experimentally demonstrated for the case of 4 log-spaced levels within the available resistance window.