Quadrature frequency divider with programmable duty cycle

A quadrature frequency divider with programmable duty cycle is presented. The circuit is intended to generate the in-phase and quadrature phase local oscillator signals for a direct conversion receiver, targetting the cellular bands around 2 GHz. The divider output duty cycle can be switched between 25% and 50% to accomodate different types of mixer topologies. Phase noise requirements are discussed to facilitate a trade-off between phase noise performance and power consumption. Simulation results are presented for a design in a 90 nm CMOS 1.3 V low power process. The quadrature divider exhibits a phase noise of -161.1 dBc/Hz in 50% duty cycle mode and -159.4 dBc/Hz in 25% duty cycle mode at 3 MHz offset frequency. It has a power consumption of 23.5 mA and 26.5 mA in 25% and 50% mode, respectively. Statistical simulations reveal an I/Q phase imbalance of less than 1 degree.