A nested digital delta-sigma modulator architecture for fractional-N frequency synthesis

A nested digital delta-sigma modulator (DDSM) architecture for fractional-N frequency synthesis is investigated and compared with the conventional MASH 1-1-1 DDSM. In the nested architecture, the LSBs of the input word are processed by a first-order DDSM and added to the MSBs before being processed by a third-order DDSM. Using the error masking design methodology [1], rules for selecting the optimum wordlengths are presented. We show that the nested architecture requires 15% fewer flip-flops and 13% fewer full-adders than the conventional architecture, resulting in an overall hardware saving of 15%. Simulation results confirm the analytical predictions.