An automatic retiming system for asynchronous fractional frequency dividers

Synchronization of the output of an asynchronous frequency divider is necessary to improve its phase noise performance, but this operation is affected by timing issue. This work presents a retiming system to avoid metastability. The system shifts the output of the divider such that its rising edge is aligned to the falling edge of the divider input signal. In this way, the resampling operation is correct for any input frequency. The proposed architecture allows power down of ancillary circuits. The system is implemented in a 65 nm CMOS technology. Mixed-signal circuit simulations demonstrate the effectiveness of the proposed solution.