SCC — A graphical tool for scripted circuit sizing of integrated CMOS-circuits based on a general description of the sizing process

Integrated CMOS-circuits are built up out of small stages which contain a few devices only. Particularly in integrated analog circuits the majority of these small stages have to be modified for every application regarding to their altered electrical boundary conditions. This usually ends up in a complete new revision of circuit sizing for the stages resp. the total circuit. However, this sizing process remains always the same in principle. The CAD-tool SCC introduced in this paper shall offer a solution to this drawback: the procedure of circuit sizing of a small and reusable CMOS-topology is implemented just once in an operational sequence description. This description contains the non-value-orientated general strategy for sizing the specific circuit topology. Sizing strategies that are captured in this way can be recalled to size the circuit automatically again even with altered boundary conditions. SCC implements the generation of the script and the simulation with specific values along with a graphical user interface for an easy to use application. Below SCC is presented at the example of sizing a symmetrical output characteristic of a push-pull inverter.