A Direct Digital Frequency Synthesizer circuit based on Dynamic Frequency Management

This paper presents the design of a Direct Digital Frequency Synthesizer (DDFS) circuit based on Dynamic Frequency Management (DFM). In this design, the clock generator circuit dynamically changes its frequency based on the required output frequency. Clock frequency is halved at low output frequencies, to reduce power consumption. Simulations are performed for 0.35 μm and 0.18 μm CMOS process resulting in about 22% and 21% power reduction, respectively. A maximum power reduction of 47% and 45% are achievable for these processes. This scheme is applicable to any DDFS circuit without any performance degradation.