An efficient algorithm for phase error minimization in phase-locked loops

An efficient semi-analytical algorithm for minimizing the rms phase error in a phase-locked loop is presented. The approach is based on an analytical description of the phase noise spectrum of fractional-N PLLs. By iterative optimization of the relevant design parameters, the minimum achievable rms phase error is calculated. The approach is illustrated for the case of four variable design parameters. Robust numerical convergence is obtained regardless of the initial conditions. Power dissipation can be reduced at the expense of a larger phase error by reducing the dimension of the parameter space during the numerical optimization.