• DocumentCode
    528826
  • Title

    Dynamic indexing: Concurrent leakage and aging optimization for caches

  • Author

    Calimera, Andrea ; Loghi, Mirko ; Macii, Enrico ; Poncino, Massimo

  • Author_Institution
    Politecnico di Torino, 10129, Torino, Italy
  • fYear
    2010
  • fDate
    18-20 Aug. 2010
  • Firstpage
    343
  • Lastpage
    348
  • Abstract
    Previous works have shown that the traditional implementations of power management (i.e., using power gating or voltage scaling) can also mitigate the aging effect induced by Negative Bias Temperature Instability (NBTI), due to the partial recovery that occurs during the idle intervals used by power management. However, such a potential has been exploited only partially because of the different nature of energy and aging: as a performance figure, aging is affected by the worst idleness pattern. Therefore, large potential energy savings usually turn into limited aging reductions. We address this problem in the context of caches, for which idleness is related to their access pattern. We propose a dynamic indexing scheme, in which the cache indexing function is changed over time in order to uniformly distribute the idleness over all the cache lines. In this way it is possible to fully use the leakage optimization potential and to extend the lifetime of a cache. Experimental analysis shows that it is possible to obtain caches that are effectively aging-free, without any penalty in leakage energy reduction.
  • Keywords
    Aging; Degradation; Indexing; Logic gates; Random access memory; Sleep; Aging; Leakage optimization; Memory Hierarchy; NBTI;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on
  • Conference_Location
    Austin, TX, USA
  • Print_ISBN
    978-1-4244-8588-8
  • Type

    conf

  • Filename
    5599049