Technology variability and uncertainty implications for power-efficient VLSI systems

Designers of power-efficient, high-performance VLSI systems have for the last several technology generations had to overcome substantial power challenges resulting from underlying technology variability and uncertainty. Microprocessor designers have responded with multicore designs to provide chip-level performance gains under the increasing power constraints. The underlying challenges due to CMOS technology will continue with increasing complexities to be managed by VLSI system designers. Fortunately improved modeling, variability-aware design, and new technology capabilities provide opportunities to overcome these difficulties. This talk will describe the most significant technology variability and modeling challenges for current and future technologies, examine current design responses, examine the risks of failing to react to the challenges, and describe new device and circuit technologies which will be available to system designers to continue to provide VLSI system efficiency gains.