DocumentCode
530147
Title
A new fault generator suitable for reliability analysis of digital circuits
Author
Marques, E.C. ; Paiva, Nilson M., Jr. ; Naviner, Lirida A B ; Naviner, Jean-François
Author_Institution
Inst. TELECOM, TELECOM ParisTech, Paris, France
fYear
2010
fDate
1-9 Oct. 2010
Firstpage
41
Lastpage
45
Abstract
This paper deals with fault injection issues for reliability analysis. We propose a fault generator IP suitable for hardware emulation of single and multiple simultaneous faults occurrence. The proposed IP is based on a very useful approach that allows the designer to control complexity and completeness of the fault injection process. We provide models for cost and performance estimation of the IP. Also, synthesis results of its implementation on FPGA are given.
Keywords
fault diagnosis; field programmable gate arrays; integrated circuit reliability; FPGA; digital circuits; fault generator IP; fault injection issues; faults occurrence; hardware emulation; reliability analysis; Circuit faults; Complexity theory; Field programmable gate arrays; Generators; IP networks; Integrated circuit reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Argentine School of Micro-Nanoelectronics Technology and Applications (EAMTA), 2010
Conference_Location
Montevideo
Print_ISBN
978-1-4244-6747-1
Electronic_ISBN
978-987-1620-14-2
Type
conf
Filename
5606377
Link To Document