A 10-Gb/s CMOS differential transimpedance amplifier for parallel optical receiver

A 10-Gb/s transimpedance amplifier (TIA) for the parallel optical receiver module is realized in 0.18-μm CMOS technology. The proposed TIA employs a regulated cascode (RGC) input structure and adopts active inductor peaking and feedback techniques to enhance the bandwidth. Besides, a noise optimization is processed. The TIA provides a conversion gain of 50 dBΩ and 3-dB bandwith of 7 GHz. The measured sensitivity is about 35 μA at a bit error rate of 10^-12 with a 2³¹-1 pseudorandom test pattern for 10 Gb/s operation. Under a 1.8-V supply voltage, the differential TIA consumes 29.2 mW, counting an output buffer. The core chip area is 144×160 μm² excluding the output buffer and testing pads.