The design and implementation of high speed manchester II bus physical interface

Manchester II coding is now widely used in many aerospace and aeronautics bus protocols. In all these protocols, the maximum data transfer rate is less than 20Mbps. Due to lack of core physical interface (PHY), higher data transfer rate can not be achieved, and key system performance can not be raised as well. To break this bottleneck, a new type fiber-optic bus PHY was designed and implemented. In addition, related simulation and debugging work was performed. In this paper, a novel sampling technique called multiple-clock-phase-shift (MCPS) is introduced. MCPS is different from traditional asynchronous serial data sampling technique such as oversampling and general clock data recovery (CDR) technique. It uses multiple stable clocks in FPGA to sample input serial data, and combines sampling bits into one output result. In the combination process of sampling results, the state transition of the FPGA logic should depend on specific bus protocol. Using MCPS technique, high speed serial data can be correctly obtained by fiber-optic bus PHY.